As the technology of electronic devices improves, so also does the technology of associated electronic memory. Specifically, digital memory devices are implemented in any of a variety of electronic devices, such as wireless communications devices and personal computers, where processing speed is constantly improving. In addition, many such electronic devices operate from battery power. As a result, the demand for memory devices that are more power efficient and achieve faster storage and access times is constantly increasing to improve battery life and to complement increases in operation and processing times of associated electronic devices.
One type of memory is flash memory, which is a type of non-volatile memory that is electronically controlled to store and erase data. Flash memory is typically configured as a flash memory transistor that includes a floating gate, such that writing data to the flash memory transistor can be accomplished via Channel Hot Electron (CHE) programming, and erasing the flash memory transistor can be accomplished via Fowler-Nordheim tunneling effects. Reading data from the flash memory can be accomplished by biasing the flash memory transistor, such that a resultant current flow on an associated bit-line that results from a charge trapped in the floating gate can be indicative of a memory value stored therein.
In a typical memory array of flash memory transistors, a source terminal of all of the flash memory transistors can be coupled together. However, the drain terminals of all of the flash memory transistors can be individually decoded via a column decoder. As an example, to read data from a typical flash memory transistor, a source terminal of the flash memory transistor is held at a negative rail voltage potential (e.g., ground), a gate terminal of the flash memory transistor is biased at approximately 5 volts, and a drain terminal is pre-charged at a bias magnitude of approximately 0.8 volts. In response, a current at the bit-line, which can be coupled to the drain terminal, can provide a current flow that is indicative of the memory value. However, the bit-line that connects the drain terminal of a flash memory transistor for a large memory array can include a substantial parasitic capacitance (e.g., 1 pF), resulting in a substantially slower pre-charge time associated with the bias magnitude at the drain terminal of the flash memory transistor. Accordingly, the access time for reading the memory value from the flash memory transistor can be slow relative to other electronic components in a system that includes a flash memory system.